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ia186xl/ia188xl data sheet 16 - bit microcontrollers july 6, 2011 ia211080711 - 09 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 1 of 75 1 - 888 - 82 4 - 4184 ia186xl/ia188xl 16 - bit microcontroller data sheet ? ?
ia186xl/ia188xl data sheet 16 - bit microcontrollers july 6, 2011 ia211080711 - 09 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 2 of 75 1 - 88 8 - 824 - 4184 copyright 2011 by innovasic semiconductor, inc. published by in novasic semiconductor, inc. 3737 princeton drive ne, suite 130, albuquerque, nm 87107 miles ? is a trademark innovasic semiconductor, inc. intel is a registered trademark of intel corporation ?
ia186xl/ia188xl data sheet 16 - bit microcontrollers july 6, 2011 ia211080711 - 09 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 3 of 75 1 - 88 8 - 824 - 4184 table of contents list of figures ................................ ................................ ................................ ................................ .. 5 list of tables ................................ ................................ ................................ ................................ ... 6 1. introduction ................................ ................................ ................................ ............................. 7 1.1 general description ................................ ................................ ................................ ....... 7 1.2 features ................................ ................................ ................................ ......................... 7 2. packaging, pin descriptions, and physical dimensions ................................ ......................... 9 2.1 packages and pinouts ................................ ................................ ................................ .... 9 2.1.1 ia186xl 68 plcc package ................................ ................................ .......... 10 2.1.2 ia188xl 68 plcc package ................................ ................................ .......... 12 2.1.3 plcc physical dimensions ................................ ................................ ............ 14 2.1.4 ia186xl 80 pqfp package ................................ ................................ ........... 15 2.1.5 ia188xl 80 pqfp package ................................ ................................ ........... 17 2.1.6 pqfp physical dimensions ................................ ................................ ............ 19 2.1.7 ia186xl 80 lqfp package ................................ ................................ ........... 20 2.1.8 ia188xl 80 lqfp package ................................ ................................ ........... 22 2.1.9 lqfp physical dimensions ................................ ................................ ............ 24 2.2 ia186xl pin/signal descriptions ................................ ................................ .............. 25 2. 3 ia188xl pin/signal descriptions ................................ ................................ .............. 31 3. maximum ratings, thermal characteristics, and dc parameters ................................ ....... 37 4. functional description ................................ ................................ ................................ .......... 39 4.1 device architecture ................................ ................................ ................................ ..... 39 4.1.1 bus interface unit ................................ ................................ ........................... 39 4.1.2 clock generator ................................ ................................ .............................. 42 4.1.3 interrupt control unit ................................ ................................ ..................... 42 4.1.4 timer/counter unit ................................ ................................ ........................ 42 4.1.5 chip - select/ready generation logic ................................ ............................. 43 4.1.6 dma ................................ ................................ ................................ ............... 44 4.1.7 dram refresh control unit ................................ ................................ .......... 44 4.1.8 power - save control ................................ ................................ ........................ 44 4.2 operating modes ................................ ................................ ................................ ......... 45 4.2.1 enhanced mode ................................ ................................ .............................. 45 4.2.2 queue status mode ................................ ................................ ......................... 45 4.2.3 once mode ................................ ................................ ................................ ... 45 4.2.4 math coprocessor (ia18 6xl only) ................................ ............................... 45 table 12. internal register map ................................ ................................ .......................... 46 5. ac specifications ................................ ................................ ................................ ................. 47 5.1 major cycle timings C read cycle ................................ ................................ ............ 47 5.2 major cycle timings C write cycle ................................ ................................ ........... 49 5.3 major cycle timings C interrupt ac knowledge cycle ................................ ............... 51 5.4 software halt cycle timings ................................ ................................ ...................... 53 5.5 clock timings ................................ ................................ ................................ ............. 55 5.6 ready, peripheral and queue status timings ................................ ............................. 56 ?
ia186xl/ia188xl data sheet 16 - bit microcontrollers july 6, 2011 ia211080711 - 09 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 4 of 75 1 - 88 8 - 824 - 4184 5.7 reset and hold/hlda timings ................................ ................................ ............... 57 6. instruction execution times ................................ ................................ ................................ . 61 7. innovasic part number cross - reference ................................ ................................ .............. 66 8. errata ................................ ................................ ................................ ................................ ..... 69 8.1 s ummary ................................ ................................ ................................ ..................... 69 8.2 detail ................................ ................................ ................................ ........................... 70 9. data sheet revision history ................................ ................................ ................................ . 74 10. fo r additional information ................................ ................................ ................................ ... 75 ?
ia186xl/ia188xl data sheet 16 - bit microcontrollers july 6, 2011 ia211080711 - 09 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 5 of 75 1 - 88 8 - 824 - 4184 list of figures figure 1. ia186xl 68 - lead plcc package diagram ................................ ................................ . 10 figure 2. ia188xl 68 - lead plcc package diagram ................................ ................................ . 12 figure 3. plcc physical package dimensions ................................ ................................ ............ 14 figure 4. ia186xl 80 - lead pqfp package diagram ................................ ................................ . 15 figure 5. ia188xl 80 - lead pqfp package diagram ................................ ................................ . 17 fi gure 6. pqfp physical package dimensions ................................ ................................ ............. 19 figure 7. ia186xl 80 - lead lqfp package diagram ................................ ................................ . 20 figure 8. ia188xl 80 - lead lqfp package diagram ................................ ................................ . 22 figure 9. lqfp physical package dimensions ................................ ................................ ............ 24 figure 10. ia186xl/ia188xl functional block diagram ................................ ......................... 41 figure 11. clock circuit connection options ................................ ................................ .............. 43 figure 12. read cycle waveforms ................................ ................................ ............................... 48 figure 13. write cycle waveforms ................................ ................................ .............................. 50 figure 14. interrupt acknowledge cycle waveforms ................................ ................................ .. 52 figure 15. software hal t cycle waveforms ................................ ................................ ................. 54 figure 16. clock waveforms ................................ ................................ ................................ ........ 58 figure 17. reset waveforms ................................ ................................ ................................ ......... 58 figure 18. synchronous ready (srdy) waveforms ................................ ................................ ... 58 figure 19. asynchronous ready (ardy) waveforms ................................ ................................ 59 figure 2 0. peripheral and queue status waveforms ................................ ................................ .... 5 9 figure 21. holda/hlda waveforms (entering hold) ................................ ............................. 60 figure 22. hold/hlda waveforms (leaving hold) ................................ ................................ 60 ?
ia186xl/ia188xl data sheet 16 - bit microcontrollers july 6, 2011 ia211080711 - 09 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 6 of 75 1 - 88 8 - 824 - 4184 list of tables table 1. ia186xl 68 - lead plcc pin listing ................................ ................................ ............. 11 table 2. ia188xl 68 - lead plcc pin listing ................................ ................................ ............. 13 table 3. ia186xl 80 - lead pqfp pin listing ................................ ................................ ............. 16 table 4. ia188xl 80 - lead pqfp pin listing ................................ ................................ ............. 18 table 5. ia186xl 80 - lead lqfp pin listing ................................ ................................ ............. 21 table 6. ia188xl 80 - lead lqfp pin listing ................................ ................................ ............. 23 table 7. ia186xl pin/signal descriptions ................................ ................................ .................. 25 table 8. ia188xl pin/signal descriptions ................................ ................................ .................. 31 table 9. ia186xl and ia188xl absolute maximum ratings ................................ ................... 37 table 10. ia186xl and ia188xl thermal characteristics ................................ ........................ 37 table 11. ia186xl and ia188xl dc parameters ................................ ................................ ...... 38 table 13. major cycle timings C read cycle ................................ ................................ ............. 47 table 14. major c ycle timings C write cycle ................................ ................................ ............. 49 table 15. major cycle timings C interrupt acknowledge cycle ................................ ................ 51 table 16. software halt cycle tim ings ................................ ................................ ....................... 53 table 17. clock timings ................................ ................................ ................................ ............... 55 table 18. ready, peripheral and queue status timings ................................ .............................. 56 table 19. reset and hold/hlda timings ................................ ................................ ................ 57 table 20. instruction set timing ................................ ................................ ................................ .. 61 table 21. innovasic part number cross - reference for the plcc ................................ ............... 66 table 22. innovasic part number cross - reference for the pqfp (special order only) .............. 67 table 23. innovasic part number cross - reference for the lqfp (special order only) ............. 68 table 24. summary of errata ................................ ................................ ................................ ........ 69 table 2 5. data sheet revision history ................................ ................................ ......................... 74 ?
ia186xl/ia188xl data sheet 16 - bit microcontrollers july 6, 2011 ia211080711 - 09 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 7 of 75 1 - 88 8 - 824 - 4184 1. introduction the innovasic semiconductor ia186xl and ia188xl microcontrollers are form, fit, and function replacements for the original intel 80c186xl and 80c188xl 16 - bit high - integration embedded processors. these devices are produced using innovasics managed ic lifetime extension system (miles?). this cloning technology, which produces replacement ics beyond simple emulations, ensures compatibility with the original device, including a ny undocumented features. additionally, the miles? process captures the clone design in such a way that production of the clone can continue even as silicon technology advances. the ia186xl and ia188xl microcontrollers replace the obsolete intel 80c186x l and 80c188xl devices, allowing users to retain existing board designs, software compilers/assemblers, and emulation tools, thereby avoiding expensive redesign efforts. 1.1 general description the innovasic semiconductor ia186xl and ia188xl microcontrollers h ave a set of base peripherals beneficial to many embedded applications and include a standard numeric interface, an interrupt control unit, a chip - select unit/ready generation logic, a dram refresh control unit, a power - save control unit, dma and three 16 - bit timer/counters. the ia186xl and ia188xl microcontrollers operate at 5.0 volts 10%. the following functional description describes the base architecture of the 80c186xl. the 80c186xl is a very high integration 16 - bit microprocessor. it combines some of the most common microprocessor system components onto one chip. the 80c186xl is object - code compatible with the 8086/8088 microprocessors and adds ten new instruction types to the 8086/8088 instruction set. the 80c186xl has two major modes of operati on, compatible and enhanced. in compatible mode , the 80c186xl is completely compatible with the 80186, with the exception of 8087 support. the enhanced mode adds three new features to the system design. these are power - save control, dynamic ram refresh, and an asynchronous numerics coprocessor interface (80c186xl only). 1.2 features the primary features of the ia186xl and ia188xl microcontrollers are as follows: form, fit, and function compatible version of the low power intel 80c186xl/80c188xl operation mo des : C enhanced mode o dram refresh control unit ?
ia186xl/ia188xl data sheet 16 - bit microcontrollers july 6, 2011 ia211080711 - 09 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 8 of 75 1 - 88 8 - 824 - 4184 o power - save mode o direct interface to 80c187 (ia 186xl only ) C compatible mode o pin - for - pin replacement f or nmos 80186/80188 non - numeric applications integrated feature set C static, modular cpu C clock generator C two inde pendent dma channels C programmable interrupt controller C three programmable 16 - bit timers C dynamic ram refresh control unit C programmable memory and peripheral chip select logic C programmable wait state generator C local bus controller C power - save mode C system - leve l testing support ( high impedance test mode ) completely object - code compatible with existing 8086/8088 software and has ten additional instructions over 8086/8088 crystal supports internal 20 C 25 mhz operation direct addressing capability to 1 mbyte memory and 64 kbyte i/o available in 68 - lead : C plastic leaded chip carrier (plcc) available in 80 - lead : C plastic quad flat pack ( p qfp) C low profile quad flat pack (lqfp) extended temperature range ( - 40c to +85c) chapter 4, functional description , provides details of the ia186xl and ia188xl microcontrollers, including the features listed above. ?
ia186xl/ia188xl data sheet 16 - bit microcontrollers july 6, 2011 ia211080711 - 09 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 9 of 75 1 - 88 8 - 824 - 4184 2. packaging , pin descriptions , and physical dimensions information on the packages and pin descriptions for the ia186xl and the ia 188xl is provided separately . refer to sections, figures, and tables for information on the device of interest. 2.1 packages and pinouts the innovasic semiconductor ia186xl and ia188 xl microcontroller is available in the following packages: 68 - lead plastic le aded chip carrier (plcc ) , equivalent to original plcc package 80 - lead plastic quad flat pack ( p qfp ) , equivalent to original pqfp package 80 - lead low profile quad flat pack (lqfp) , equivalent to original s qfp package ?
ia186xl/ia188xl data sheet 16 - bit microcontrollers july 6, 2011 ia211080711 - 09 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 10 of 75 1 - 88 8 - 824 - 4184 2.1.1 ia186xl 68 plcc package the pinout for the ia186xl 68 plcc package is as shown in figure 1 . the corresponding pinout is provided in table 1 . figure 1 . ia186xl 68 - lead plcc package diagram ?
ia186xl/ia188xl data sheet 16 - bit microcontrollers july 6, 2011 ia211080711 - 09 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 11 of 75 1 - 88 8 - 824 - 4184 table 1 . ia186xl 68 - lead plcc pin listing pin nam e pin name pin name pin name 1 ad15 18 drq0 35 mcs3_n / nps_n 52 s0_n 2 ad7 19 drq1 36 mcs2_n 53 s1_n 3 ad14 20 tmr in 0 37 mcs1 _n / error_n 54 s2_n 4 ad6 21 tmr in 1 38 mcs0_n / pereq 55 ardy 5 ad13 22 tmr out 0 39 den_n 56 clkout 6 ad5 23 tmr out 1 40 dt / r_n 57 reset 7 ad12 24 res_n 41 int3 / inta1_n 58 x2 8 ad4 25 pcs0_n 42 int2 / inta0_n 59 x1 9 v cc 26 v ss 43 v cc 60 v ss 10 ad11 27 pcs1_n 44 int1 / select_n 61 ale / qs0 11 ad3 28 pcs2_n 45 int0 62 rd_n / qsmd_n 12 ad 10 29 pcs3_n 46 nmi 63 wr_n / qs1 13 ad2 30 pcs4_n 47 test_n /busy 64 bhe _n 14 ad9 31 pcs5_n / a 1 48 lock_n 65 a19 / s6 15 ad1 32 pcs6_n / a 2 49 s rdy 66 a18 / s5 16 ad8 33 lcs_n 50 hold 67 a17 / s4 17 ad0 34 ucs_n 51 hlda 68 a16 / s3 ?
ia186xl/ia188xl data sheet 16 - bit microcontrollers july 6, 2011 ia211080711 - 09 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 12 of 75 1 - 88 8 - 824 - 4184 2.1.2 ia188xl 68 plcc package the pinout for the ia188xl 68 plcc package is as shown in figure 2 . the corresponding pinout is provided in table 2 . note: the innovasic 68 - lead plcc package has both an ink mark and an indentation to indicate proper orientation. pin 1 is designated by the ink mark, as shown in figure 2. figure 2 . ia188xl 68 - lead plcc package diagram ink mark (pin 1 indicator ) ?
ia186xl/ia188xl data sheet 16 - bit microcontrollers july 6, 2011 ia211080711 - 09 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 13 of 75 1 - 88 8 - 824 - 4184 table 2 . ia188xl 68 - lead plcc pin listing pin name pin name pin name pin name 1 a15 18 drq0 35 mcs3_n/nps_n 52 s0_n 2 ad7 19 drq1 36 mcs2_n 53 s1_n 3 a14 20 tmr in 0 37 mcs1 _n/error_n 54 s2_n 4 ad6 21 tmr in 1 38 mcs0 _n/pereq 55 ardy 5 a13 22 tmr out 0 39 den_n 56 clkout 6 ad5 23 tmr out 1 40 dt/r_n 57 reset 7 a12 24 res _n 41 int3/inta1_n 58 x2 8 ad4 25 pcs0_n 42 int2/inta0_n 59 x1 9 v cc 26 v ss 43 v cc 60 v ss 10 a11 27 pcs1_n 44 int1/select_n 61 ale/qs0 11 ad3 28 pcs2_n 45 int0 62 rd _n/qsmd_n 12 a10 29 pcs3_n 46 nmi 63 wr _n/qs1 13 ad2 30 pcs4_n 4 7 test_n /busy 64 rfsh_n 14 a9 31 pcs5_n/ a 1 48 lock_n 65 a19/s6 15 ad1 32 pcs6 _n/ a 2 49 srdy 66 a18/s5 16 a8 33 lcs_n 50 hold 67 a17/s4 17 ad0 34 ucs_n 51 hlda 68 a16/s3 ?
ia186xl/ia188xl data sheet 16 - bit microcontrollers july 6, 2011 ia211080711 - 09 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 14 of 75 1 - 88 8 - 824 - 4184 2.1.3 plcc physical dimensions the physical dimensions for the 68 plcc are as shown in figure 3 . figure 3 . p lcc physical pac kage dimensions legend: symbol min nom 1 max c C 0.008 C d C 0.990 C d1 C 0.953 C d2 C 0.910 d3 C 0.800 C e C 0.990 C e1 C 0.953 C e2 C 0.910 C e3 C 0.800 C note: controlling dime nsion in inches. note: 1 controlling dimension in inches. 1. datums d C e and f C g to be determined where center leads exit plastic body at datum plane C h C . 2. datum plane C h C located at top of mold parting line and coincident with top of lead. where lead exits plastic body. ?
ia186xl/ia188xl data sheet 16 - bit microcontrollers july 6, 2011 ia211080711 - 09 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 15 of 75 1 - 88 8 - 824 - 4184 2.1.4 ia186xl 80 pqfp package the pinout for the ia186xl 80 pqfp package is as shown in figure 4 . the corresponding pinout is provided in table 3 . figure 4 . ia186xl 80 - lead p qfp package diagram ?
ia186xl/ia188xl data sheet 16 - bit microcontrollers july 6, 2011 ia211080711 - 09 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 16 of 75 1 - 88 8 - 824 - 4184 table 3 . ia186xl 80 - lead p qfp pin listing pin name pin name pin name pin name 1 ad15 21 s2_n 41 mcs2_n 61 drq0 2 n.c. 22 s1_n 42 mcs3_n / nps_n 62 n.c. 3 a16/s3 23 s0_n 43 n.c. 63 n.c. 4 a17/s4 24 n.c. 44 n.c. 64 ad0 5 a18/s5 25 hld a 45 ucs_n 65 ad8 6 a19/s6 26 hold 46 lcs_n 66 ad1 7 bhe_n 27 srdy 47 pcs6 _n / a2 67 ad9 8 wr_n/qs1 28 lock_n 48 pcs5_n / a1 68 ad2 9 rd_n/qsmd_n 29 test_n /busy 49 pcs4_n 69 ad10 10 ale/qs0 30 nmi 50 pcs3_n 70 ad3 11 n.c. 31 int0 51 pcs2_n 71 ad11 12 v ss 32 int1 / select_n 52 pcs1_n 72 v cc 13 v ss 33 v cc 53 v ss 73 v cc 14 n.c. 34 v cc 54 pcs0_n 74 ad4 15 n.c. 35 int2 / inta0_n 55 res_n 75 ad12 16 x1 36 int3 / inta1_n 56 tmr out 1 76 ad5 17 x2 37 dt / r_n 57 tmr out 0 77 ad13 18 reset 38 den_n 58 tmr in 1 78 ad6 19 clkout 39 mcs0 _n / pereq 59 tmr in 0 79 ad14 20 ardy 40 mcs1 _n / error_n 60 drq1 80 ad7 ?
ia186xl/ia188xl data sheet 16 - bit microcontrollers july 6, 2011 ia211080711 - 09 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 17 of 75 1 - 88 8 - 824 - 4184 2.1.5 ia188xl 80 pqfp package the pinout for the ia186xl 80 pqfp package is as shown in figure 5 . the correspond ing pinout is provided in table 4 . figure 5 . ia188xl 80 - lead p qfp package diagram ?
ia186xl/ia188xl data sheet 16 - bit microcontrollers july 6, 2011 ia211080711 - 09 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 18 of 75 1 - 88 8 - 824 - 4184 table 4 . ia188xl 80 - lead p qfp pin listing pin name pin name pin name pin name 1 a15 21 s2_n 41 mcs2_n 61 drq0 2 n .c. 22 s1_n 42 mcs3_n/nps_n 62 n.c. 3 a16/s3 23 s0_n 43 n.c. 63 n.c. 4 a17/s4 24 n.c. 44 n.c. 64 ad0 5 a18/s5 25 hlda 45 ucs_n 65 a8 6 a19/s6 26 hold 46 lcs_n 66 ad1 7 rfsh_n 27 srdy 47 pcs6 _n/a2 67 a9 8 wr_n/qs1 28 lock_n 48 pc s5_n/a1 68 ad2 9 rd_n/qsmd_n 29 test_n /busy 49 pcs4_n 69 a10 10 ale/qs0 30 nmi 50 pcs3_n 70 ad3 11 n.c. 31 int0 51 pcs2_n 71 a11 12 v ss 32 int1/select_n 52 pcs1_n 72 v cc 13 v ss 33 v cc 53 v ss 73 v cc 14 n.c. 34 v cc 54 pcs0_n 74 ad4 15 n.c. 35 int2/inta0_n 55 res_n 75 a12 16 x1 36 int3/inta1_n 56 tmr out 1 76 ad5 17 x2 37 dt/r_n 57 tmr out 0 77 a13 18 reset 38 den_n 58 tmr in 1 78 ad6 19 clkout 39 mcs0 _n/pereq 59 tmr in 0 79 a14 20 ardy 40 mcs1 _n/error_n 60 dr q1 80 ad7 ?
ia186xl/ia188xl data sheet 16 - bit microcontrollers july 6, 2011 ia211080711 - 09 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 19 of 75 1 - 88 8 - 824 - 4184 2.1.6 pqfp physical dimensions the physical dimensions for the 80 p qfp are as shown in figure 6 . figure 6 . pqfp physical package dime nsions legend: symbol millimeter inch min nom max min nom max a C C 3.40 C C 0.134 a1 0.25 C C 0.010 C C a2 2.55 2.72 3.05 0.100 0.107 0.120 d 23.9 0 basic 0.941 basic d1 20.00 basic 0.787 basic e 17.90 basic 0.705 basic e1 14.00 basic 0.551 basic r2 0.013 C 0.30 0.005 C 0.012 r1 0.013 C C 0.005 C C 0 3.5 7 0 3.5 7 1 0 C C 0 C C 2, 3 a 7 ref 7 ref 2, 3 b 15 ref 15 ref c 0.11 0.15 0.23 0.004 0.006 0.009 l 0.73 0.88 1.03 0.029 0.035 0.041 l1 1.95 ref 0.077 ref s 0.40 C C 0.016 C C b 0.30 0.35 0.45 0.012 0.014 0.018 e 0.80 bsc 0 .031 bsc d2 18.40 ref 0.724 e2 12.00 ref 0.472 tolerances of form and position aaa 0.25 0.010 bbb 0.20 0.008 ccc 0.20 0.008 a alloy 42 l/f. b copper l/f. notes : 1. dimension d1 and e1 do not include mold protrusion. allowable protrusion is 0.25mm per side. dimension d1 and e1 do not include mold mismatch an d are determined a datum plane C h C . 2. dimension b does not include dambar protrusion. allowable dambar protrusion will not cause the lead width to exceed the maximum b dimension by more than 0.08mm. dambar cannot be located on the lower radius of the lead foot. ?
ia186xl/ia188xl data sheet 16 - bit microcontrollers july 6, 2011 ia211080711 - 09 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 20 of 75 1 - 88 8 - 824 - 4184 2.1.7 ia186xl 80 lqfp package the pinout for the ia186xl 80 lqfp package is as shown in figure 7 . the corresponding pinout is provided in table 5 . figure 7 . ia186xl 80 - lead lqfp package diagram ?
ia186xl/ia188xl data sheet 16 - bit microcontrollers july 6, 2011 ia211080711 - 09 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 21 of 75 1 - 88 8 - 824 - 4184 table 5 . ia186xl 80 - lead lqfp pin listing pin name pin name pin name pin name 1 ad0 21 a16/s3 41 v ss 61 v cc 2 ad8 22 a17/s4 42 hlda 62 ucs_n 3 ad1 23 a18/s5 43 hold 63 lcs_n 4 n.c. 24 a19/s6 44 srdy 64 pcs6_n/a2 5 ad9 25 n.c. 45 lock_n 65 pcs5_n/a1 6 ad2 26 bhe_n 46 test_n/busy 66 pcs4_n 7 ad10 27 wr_n/qs1 47 nmi 67 pcs3_n 8 ad3 28 rd_n/qsmd_n 48 int0 68 pcs2_n 9 ad11 29 ale/qs0 49 int1/select_n 69 pcs1_n 10 v cc 30 v ss 50 v cc 70 v ss 11 v cc 31 v ss 51 v cc 71 pcs0_n 12 ad4 32 x1 52 int2/inta0_n 72 n.c. 13 ad12 33 x2 53 int3/inta1_n 73 res_n 14 ad5 34 reset 54 dt/r_n 74 tmr out 1 15 ad13 35 n.c. 55 n.c. 75 tmr out 0 16 ad6 36 clkout 56 den_n 76 tmr in 1 17 ad14 37 ardy 57 mcs0_n/pereq 77 tmr in 0 18 ad7 38 s2_n 58 mcs1_n/error 78 dqr1 19 ad15 39 s1_n 59 mcs2_n 79 dqr0 20 v cc 40 s0_n 60 mcs3_n/nps_n 80 v ss ?
ia186xl/ia188xl data sheet 16 - bit microcontrollers july 6, 2011 ia211080711 - 09 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 22 of 75 1 - 88 8 - 824 - 4184 2.1.8 ia188xl 80 lqfp package the pinout for the ia188xl 80 lqfp package is as shown in figure 8 . the corresponding pinout is provi ded in table 6 . figure 8 . ia188xl 80 - lead lqfp package diagram ?
ia186xl/ia188xl data sheet 16 - bit microcontrollers july 6, 2011 ia211080711 - 09 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 23 of 75 1 - 88 8 - 824 - 4184 table 6 . ia188xl 80 - lead lqfp pin listing pin name pin name pin name pin name 1 ad0 21 a16/s3 41 v ss 61 v cc 2 a8 22 a17/s4 42 hlda 62 ucs_n 3 ad1 23 a18/s5 43 hold 63 lcs_n 4 n.c. 24 a19/s6 44 srdy 64 pcs6_n/a2 5 a9 25 n.c. 45 lock_n 65 pcs5_n/a1 6 ad2 26 rfsh_n 46 test_n/busy 66 pcs4_n 7 a10 27 wr_n/qs1 47 nmi 67 pcs3_n 8 ad3 28 rd_n/qsmd_n 48 int0 68 pcs2_n 9 a11 29 ale/qs0 49 int1/select_n 69 pcs1_n 10 v cc 30 v ss 50 v cc 70 v ss 11 v cc 31 v ss 51 v cc 71 pcs0_n 12 ad4 32 x1 52 int2/inta0_n 72 n.c. 13 a12 33 x2 53 int3/inta1_n 73 res_n 14 ad5 34 reset 54 dt/r_n 74 tmr out 1 15 a13 35 n. c. 55 n.c. 75 tmr out 0 16 ad6 36 clkout 56 den_n 76 tmr in 1 17 a14 37 ardy 57 mcs0_n/pereq 77 tmr in 0 18 ad7 38 s2_n 58 mcs1_n/error 78 dqr1 19 a15 39 s1_n 59 mcs2_n 79 dqr0 20 v cc 40 s0_n 60 mcs3_n/nps_n 80 v ss ?
ia186xl/ia188xl data sheet 16 - bit microcontrollers july 6, 2011 ia211080711 - 09 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 24 of 75 1 - 88 8 - 824 - 4184 2.1.9 lqfp physical dimensions the physical dimensions for the 80 lqfp are as shown in figure 9 . figure 9 . lqfp physical package dimensions legend: symbol dimension in mm dimension in inch min nom max min n om max a C C 1.60 C C 0.063 a 1 0.05 C 0.15 0.002 C 0.006 a 2 1.35 1.40 1.45 0.053 0.055 0.057 b 0.17 0.22 0.27 0.007 0.009 0.011 b 1 0.17 0.20 0.23 0.007 0.008 0.009 c 0.09 C 0.20 0.004 C 0.008 c 1 0.09 C 0.16 0.004 C 0.006 d 14.00 bsc 0.551 bsc d 1 12.00 bsc 0.472 bsc e 14.00 bsc 0.551 bsc e 1 12.00 bsc 0.472 bsc e 0.50 bsc 0.020 bsc l 0.45 0.60 0.75 0. 018 0.024 0.030 l 1 1.00 ref 0.039 ref r 1 0.08 C C 0.003 C C r 2 0.08 C 0.20 0.003 C 0.008 s 0.20 C C 0.008 C C 0 3.5 7 0 3.5 7 1 0 C C 0 C C 2 11 12 13 11 12 13 3 11 12 13 11 12 13 notes : 1 . exact shape of each corner is optional. 2 . control ling dimension: mm. 1. to be determined at seating plane c. 2. dimensions d1 and e1 do not include mold protrusion. d1 and e1 are maximum plastic body size dimensions including mold mismat ch. 3. dimension b does not include dambar protrusion. dambar cannot be located on the lower radius of the foot. 4. exact shape of each corner is optional. 5. these dimensions apply to the flat se ction of the lead between 0.10 and 0.25mm from the lead tip . 6. a1 is defined as the distance from the seating plane to the lowest point of the package body. ?
ia186xl/ia188xl data sheet 16 - bit microcontrollers july 6, 2011 ia211080711 - 09 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 25 of 75 1 - 88 8 - 824 - 4184 2.2 ia186xl pin/signal descriptions descriptions of the pin and signal functions for the ia186xl microcontroller are provided in table 7 . several of the ia186xl pins have different functions depending on the operating mode of the device. each of the different signals supported by a pin is listed and defined in table 7 , indexed alphabetically in the first column of the table. additionally, the name of the pin asso ciated with the signal as well as the pin numbers for the plcc, p qfp, and lqfp packages are provided in the pin column. signals not used in a specific package type are designated na. table 7 . ia186xl pin/signal descriptions signal pin description name plcc p qfp lqfp a1 pcs5_n / a1 31 48 65 latched address bit a1 . output. a2 pcs6_n / a2 32 47 64 latched address bit a2 . output. a16 a16 / s3 68 3 21 a ddress bits 16 C 19 . output. these pins provide the four most - signif icant bits of the address bus during t 1 only. during t 2 , t 3 , t w and t 4 they provide bus status . a17 a17 / s4 67 4 22 a18 a18 / s5 66 5 23 a19 a19 / s6 65 6 24 ad0 ad0 17 64 1 a ddress/ d ata bits 0 C 15 . input/output. these pins provide the multiplexed address bus and data bus. during the address portion of the ia186xl bus cycle, address bits [0 C 15 ] are presented on the bus and can be latched using the ale signal (see next table e ntry). during the data portion of the bus cycle, data are present on these lines. ad1 ad1 15 66 3 ad2 ad2 13 68 6 ad3 ad3 11 70 8 ad4 ad4 8 74 12 ad5 ad5 6 76 14 ad6 ad6 4 78 16 ad7 ad7 2 80 18 ad8 ad8 16 65 2 ad9 ad9 14 67 5 ad10 ad10 12 69 7 ad11 ad11 10 71 9 ad12 ad12 7 75 13 ad13 ad13 5 77 15 ad14 ad14 3 79 17 ad15 ad15 1 1 19 ?
ia186xl/ia188xl data sheet 16 - bit microcontrollers july 6, 2011 ia211080711 - 09 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 26 of 75 1 - 88 8 - 824 - 4184 table 7 . ia186xl pin/signal descriptions (continued) signal pin description name plcc p qfp lqfp ale ale / qs0 61 10 29 a ddress l atch e nable. o utput. active high. this signal is used to latch valid address information on the falling edge of ale during the address portion of a bus cycle. ardy ardy 55 20 37 a synchronous r ea dy . input. indicates to the processor the addressed memory space or i/o d evice will complete the transfer . bhe_n bhe_n 64 7 26 b yte h igh e nable. output. active low. when bhe_n is asserted (low), it indicates that the bus cycle in progress is transferring data over the upper half of the data bus. additionally, bhe_n and ad 0 encode the following bus information: ad0 bhe_n bus status 0 0 word transfer 0 1 even byte transfer 1 0 odd byte transfer 1 1 refresh operation (enhanced mode) note: bhe_n is used as refresh_n in the ia188xl . busy tes t_n /busy 47 29 46 busy . input. active high. used in enhanced mode. when the busy input is asserted, it causes the ia186xl to suspend operation during the execution of the intel 80c187 numerics coprocessor instructions. operation resumes when the pin is sampled low. clkout clkout 56 19 36 cl oc k ou tput. output. the clkout pin provides a timing reference for inputs and outputs of the ia186xl. this clock output is one - half the input clock ( clkin ) frequency. the clkout signal has a 50% duty cycle, trans itioning every falling edge of clkin . den_n den_n 39 38 56 d ata en able. output. active low. this signal is used to enable bidirectional trans ceivers in a buffered system. the den_n signal is asserted (low) only when data are to be transferred on the b us. drq0 drq0 18 61 79 d ma r e q uest 0 or 1 . input. a sserted high by an external device to request dma channel 0 or 1 to perform a transfer. these signals are level - triggered and internally synchronized . drq1 drq1 19 60 78 ?
ia186xl/ia188xl data sheet 16 - bit microcontrollers july 6, 2011 ia211080711 - 09 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 27 of 75 1 - 88 8 - 824 - 4184 table 7 . ia186xl pin/signal descriptions (continued) signal pin description name plcc p qfp lqfp dt/r_n dt/r_n 40 37 54 d ata t ransmit /r eceive. output. this signal is used to control the direction of data flow for bidirectional buffers in a buffered system. when dt/r_n is high, the direction indicated is transmit; when dt/r_n is low, the direction indicated is receive. error_n mcs1 _n / error_n 37 40 58 error . input. active low. when this signal is asserted (low), it indicates that the last numerics coprocessor operation resulte d in an exception condition . hlda hlda 51 25 42 h o ld a cknowledge. output. active high. when hlda is asserted (high), it indicates that the ia186xl has relinquished control of the local bus to another bus master in response to a hold request (see next t able entry). when hlda is asserted, the ia186xl data bus and control signals are floated allowing another bus master to drive the signals directly. hold hold 50 26 43 hold . input. active high. this signal is a request indicating that an external bus m aster wishes to gain control of the local bus. the ia186xl will relinquish control of the local bus between instruction boundaries not conditioned by a lock prefix. int0 int0 45 31 48 int errupt n (n = 0 C 3 ). input. active high. these maskable inputs in terrupt program flow and cause execution to continue at an interrupt vector of a specific interrupt type as follows: int0 : type 12 int1 : type 13 int2 : type 14 int3 : type 15 to allow interrupt expansion, int0 and int1 can be used with the interrupt ac knowledge signals inta0_n and inta1_n (see next table entries). int1 int1 44 32 49 int2 int2/inta0_n 42 35 52 int3 int3/inta1_n 41 36 53 inta 0_n int2/inta0_n 42 35 52 int errupt a cknowledge . output. active low . w hen used with external interrupt cont rollers. int a 1_n int3/inta1_n 41 36 53 ?
ia186xl/ia188xl data sheet 16 - bit microcontrollers july 6, 2011 ia211080711 - 09 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 28 of 75 1 - 88 8 - 824 - 4184 table 7 . ia186xl pin/signal descriptions (continued) signal pin description name plcc p qfp lqfp lcs_n lcs_n 33 46 63 l ower c hip s elect. output. active low. this pin provides a chip select signal that will be asserted (low) whenever the address of a memory bus cycle is within the address space programmed for that output. lock_n lock_n 48 28 45 lock . output. active low. when asserted (low), this signal indicates that the bus cycle in progress cannot be i nterrupted. while lock_n is active, the ia186xl will not service bus requests such as hold. when resin_n is active, this pin is weakly held high and must not be driven low. mcs0_n mcs0_n / pereq 38 39 57 m id - range memory c hip s elect . output . mcs1 _n mcs1 _ n / error_n 37 40 58 mcs2_n mcs2_n 36 41 59 mcs3_n mcs3_n / nps_n 35 42 60 n.c. n.c. na 2, 11, 14, 15, 24, 43, 44, 62, 63 4, 25, 35, 55, 72 n ot c onnected . nmi nmi 46 30 47 n on - m askable i nterrupt. input. active high. when the nmi signal is asserted (h ig h) it causes a type 2 interrupt . nps_n mcs3_n / nps_n 35 42 60 n umeric p rocessor s elect pcs0_n pcs0_n 25 54 71 p eripheral c hip s elect signals 0 C 6 . output . pcs1_n pcs1_n 27 52 69 pcs2_n pcs2_n 28 51 68 pcs3_n pcs3_n 29 50 67 pcs4_n pcs4_n 30 49 66 pcs5_n pcs5_n / a1 31 48 65 pcs6_n pcs6_n / a2 32 47 64 pereq mcs0_n / pereq 38 39 57 numerics co p rocessor e xternal req uest. input. active high. when asserted (high), this signal indicates that a data transfer between an intel 80c187 numerics coprocesso r and the cpu is pending. ?
ia186xl/ia188xl data sheet 16 - bit microcontrollers july 6, 2011 ia211080711 - 09 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 29 of 75 1 - 88 8 - 824 - 4184 table 7 . ia186xl pin/signal descriptions (continued) signal pin description name plcc p qfp lqfp qs0 ale / qs0 61 10 29 q ueue s tatus 0 , q ueue s tatus 1 . output. qs1 qs0 0 0 no queue operations 0 1 first byte of opcode pulled from queue 1 1 additional bytes pulled from queue 1 0 queue is flushed qs1 wr_n / qs1 63 8 27 qsmd_n rd_n / qsmd_n 62 9 28 q ueue s tatus m o d e . inpu t. sampled at reset. rd_n rd_n / qsmd_n 62 9 28 r ea d . output. active low. when asserted (low), rd_n indicates that the accessed memory or i/o device must drive data from the location being accessed onto the data bus. res_n res_n 24 55 73 res_n . input. f orces the processor to terminate present activity, reset the internal logic, and enter a dormant state until res_n goes high . reset reset 57 18 34 reset is an output signal in dicating the cpu is being reset. it can be used as a system reset . s0_n s0_n 52 23 40 s tatu s [ 2 : 0 ] _n are o utput s . during a bus cycle , the status (i.e., type) of cycle is encoded on these lines as follows: s2_n s1_n s0_n bus cycle status 0 0 0 interrupt acknowledge 0 0 1 read i/o 0 1 0 write i/o 0 1 1 processor halt 1 0 0 queu e instruction fetch 1 0 1 read memory 1 1 0 write memory 1 1 1 no bus activity s1_n s1_n 53 22 39 s2_n s2_n 54 21 38 s3 a16 / s3 68 3 21 s tatu s [ 6 : 3 ] are o utput s . bus cycle a19/s 6 a18/s 5 a17/s 4 a16/s 3 t 1 a19 a18 a17 a16 t 2 n 0 0 0 t 3 n 0 0 0 t w n 0 0 0 t 4 n 0 0 0 ____________ n = 0 for cpu bus cycle. n = 1 for dma or refresh cycle. s4 a17 / s4 67 4 22 s5 a18 / s5 66 5 23 s6 a19 / s6 65 6 24 srdy srdy 49 27 44 s ynchronous r ea dy . input. ?
ia186xl/ia188xl data sheet 16 - bit microcontrollers july 6, 2011 ia211080711 - 09 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 30 of 75 1 - 88 8 - 824 - 4184 table 7 . ia186xl pin/signal descriptions (continued ) signal pin description name plcc p qfp lqfp test_n test_n/busy 47 29 46 test . input. active low. when the test_n input is high (i.e., not asserted), it causes the ia186xl to suspend operation during the execution of the wait instruction. operation resumes when the pin is sampled low (asserted). tmr in 0 tmr in 0 20 59 77 t i m e r 0 in put. input. depending on the timer mode programmed for timer 0, this input is used either as clock input or a control signal. tmr in 1 tmr in 1 21 58 76 t imer 1 in put . input. depending on the timer mode programmed for timer 1, this input is used either as clock input or a control signal. tmr out 0 tmr out 0 22 57 75 t i m e r 0 out put. output. depending on the timer mode programmed for timer 0, this output can provide a single pulse or a repetitive waveform. tmr out 1 tmr out 1 23 56 74 t imer 1 out put. output. depending on the timer mode programmed for timer 1, this output can provide a single clock or a repetitive waveform. ucs_n ucs_n 34 45 62 u pper c hip s elect. output. active low. this pin provides a chip select signal that will be asserted (low) whenever the address of a memory bus cycle is within the address space programmed for that output. v cc v cc 9, 43 33, 34, 72, 73 10, 11, 20, 50, 51, 61 power ( v cc ). this pin provides power for the ia186xl device. it must be connected to a +5v dc power source. v ss v ss 26, 60 12, 13, 53 30, 31, 41, 70, 80 ground ( v ss ). this pin provides the digital ground (0v) for the ia186xl. it must be connected to a v ss board pla ne. wr_n wr_n / qs1 63 8 27 wr ite. output. active low. when asserted (low), wr_n indicates that data available on the data bus are to be latched into the accessed memory or i/o device. x1 x1 59 16 32 x1 and x2 are inputs for the crystal x2 x2 58 17 33 ?
ia186xl/ia188xl data sheet 16 - bit microcontrollers july 6, 2011 ia211080711 - 09 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 3 1 of 75 1 - 88 8 - 824 - 4184 2.3 ia188xl pin/signal descriptions descriptions of the pin and signal functions for the ia188xl microcontroller are provided in table 8 . several of the ia188xl pins have different functions depending on the operat ing mode of the device. each of the different signals supported by a pin is listed and defined in table 8 , indexed alphabetically in the first column of the table. additionally, the name of the pin associated wit h the signal as well as the pin numbers for the plcc, qfp, and lqfp packages ar e provided in the pin column. table 8 . ia188xl pin/signal de scriptions signal pin description name plcc p qfp lqfp a1 pcs5_n / a1 31 48 65 latched address bit a1 . output. a2 pcs6_n / a2 32 47 64 latched address bit a2 . output. a16 a16 / s3 68 3 21 a ddress bits 16 C 19 . output. these pins provide the four most - signifi cant bits of the address bu s during t 1 only. during t 2 , t 3 , t w and t 4 they provide bus status. a17 a17 / s4 67 4 22 a18 a18 / s5 66 5 23 a19 a19 / s6 65 6 24 ad0 ad0 17 64 1 a ddress/ d ata bits 0 - 15 . input/output. these pins provide the multiplexed addre ss bus and data bus. during the address portion of the ia18 8 xl bus cycle, address bits 0 through 15 are presented on the bus and can be latched using the ale signal (see next table entry). during the data portion of the ia18 8 xl bus cycle, data are presen t on these lines. ad1 ad1 15 66 3 ad2 ad2 13 68 6 ad3 ad3 11 70 8 ad4 ad4 8 74 12 ad5 ad5 6 76 14 ad6 ad6 4 78 16 ad7 ad7 2 80 18 a8 a8 16 65 2 valid address information is provided for the entire bus cycle a9 a9 14 67 5 a10 a10 12 69 7 a11 a11 10 71 9 a12 a12 7 75 13 a13 a13 5 77 15 a14 a14 3 79 17 a15 a15 1 1 19 ?
ia186xl/ia188xl data sheet 16 - bit microcontrollers july 6, 2011 ia211080711 - 09 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 32 of 75 1 - 88 8 - 824 - 4184 table 8. ia188xl pin/signal descriptions (continued) signal pin description name plcc p qfp lqfp ale ale / qs0 61 10 29 a ddress l atch e nable. output. active high . this signal is used to latch address information during the address portion of a bus cycle. ardy ardy 55 20 37 a synchronous r ea dy . input. indicates to the processor the addressed memory space or i/o device will complete the transfer . clkout clkout 56 1 9 36 cl oc k ou tput. output. the clkout pin provides a timing reference for inputs and outputs of the ia18 8 xl. this clock output is one - half the input clock ( clkin ) frequency. the clkout signal has a 50% duty cycle, transitioning every falling edge of cl kin . den_n den_n 39 38 56 d ata en able. output. active low. this signal is used to enable bidirectional transceivers in a buffered system. the den_n signal is asserted (low) only when data are to be transferred on the bus. drq0 drq0 18 61 79 d ma r e q ue st 0 or 1 . input. a sse rted high by an external device to request dma channel 0 or 1 to perform a transfer. these signals are level - triggered and internally synchronized drq1 drq1 19 60 78 dt/r_n dt/r_n 40 37 54 d ata t ransmit /r eceive. output. this sig nal is used to control the direction of data flow for bidirectional buffers in a buffered system. when dt/r_n is high, the direction indicated is transmit; when dt/r_n is low, the direction indicated is receive. ?
ia186xl/ia188xl data sheet 16 - bit microcontrollers july 6, 2011 ia211080711 - 09 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 33 of 75 1 - 88 8 - 824 - 4184 table 8. ia188xl pin/signal descriptions (continued) signal pin description name plcc p qfp lqfp hlda hlda 51 25 42 h o ld a cknowledge. output. active high. when hlda is asserted (high), it indicates that the ia18 8 xl has relinquished control of the local bus to another bus master in response to a hold request (see next table entry). when hlda is asserted, the ia18 8 xl data bus and control signals are floated allowing another bus master to drive the signals directly. hold hold 50 26 43 hold . input. active high. this signal is a request ind icating that an external bus master wishes to gain control of the local bus. the ia18 8 xl will relinquish control of the local bus between instruction boundaries not conditioned by a lock prefix. int0 int0 45 31 48 int errupt n (n = 0 3 ). input. active hi gh. these maskable inputs interrupt program flow and cause execution to continue at an interrupt vector of a specific interrupt type as follows: int0 : type 12 int1 : type 13 int2 : type 14 int3 : type 15 to allow interrupt expansion, int0 and int1 can be used with the interrupt acknowledge signals inta0_n and inta1_n (see next table entries). int1 int1 44 32 49 int2 int2/inta0_n 42 35 52 int3 int3/inta1_n 41 36 53 inta 0_n int2/inta0_n 42 35 52 int errupt a cknowledge . output. active low . w hen used with external interrupt controllers. int a 1_n int3/inta1_n 41 36 53 lcs_n lcs_n 33 46 63 l ower c hip s elect. output. active low. this pin provides a chip select signal that will be asserted (low) whenever the address of a memory bus cycle is within t he address space programmed for that output. ?
ia186xl/ia188xl data sheet 16 - bit microcontrollers july 6, 2011 ia211080711 - 09 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 34 of 75 1 - 88 8 - 824 - 4184 table 8. ia188xl pin/signal descriptions (continued) signal pin description name plcc p qfp lqfp lock_n lock_n 48 28 45 lock . output. active low. when asserted (low), this signal indicates that the bus cycle in progress cannot be interrupted. while lock_n is active, the ia18 8 xl will not service bus requests such as hold. when resin_n is active, this pin is weakly held high and must not be driven low. mcs0_n mcs0_n / pereq 38 39 57 m id - range memory c hip s elect . output . mcs1 _n mcs1 _n / error_n 37 40 58 mcs2_n mcs2_n 36 41 59 mcs3_n mcs3_n / nps_n 35 42 60 n.c. n.c. na 2, 11, 14, 15, 24, 43, 44, 62, 63 4, 25, 35, 55, 72 n ot c onnected nmi nmi 46 30 47 n on - m askable i nterrupt. input. active high. when t he nmi signal is asserted (high) it causes a type 2 interrupt . pcs0_n pcs0_n 25 54 71 p eripheral c hip s elect signals 0 C 6 . output . pcs1_n pcs1_n 27 52 69 pcs2_n pcs2_n 28 51 68 pcs3_n pcs3_n 29 50 67 pcs4_n pcs4_n 30 49 66 pcs5_n pcs5_n / a1 31 48 65 pcs6_n pcs6_n / a2 32 47 64 qs0 ale / qs0 61 10 29 q ueue s tatus 0 , q ueue s tatus 1 . output. qs1 qs0 0 0 no queue operations 0 1 first byte of opcode pulled from queue 1 1 additional by tes pulled from queue 1 0 queue is flushed qs1 wr_n / qs1 63 8 27 qsmd_n rd_n/qsmd_n 62 9 28 q ueue s tatus m o d e . input. sampled at reset. rd_n rd_n / qsmd_n 62 9 28 r ea d . output. active low. when asserted (low), rd_n i ndicates that the accessed memory or i/o device must drive data from the location being accessed onto the data bus. ?
ia186xl/ia188xl data sheet 16 - bit microcontrollers july 6, 2011 ia211080711 - 09 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 35 of 75 1 - 88 8 - 824 - 4184 table 8. ia188xl pin/signal descriptions (continued) signal pin description name plcc p qfp lqfp res_n res_n 24 55 73 res_n . input. fo rces the processor to terminate its present activity, reset the internal logic, and enter a dormant state until res_n goes high . reset reset 57 18 34 reset is an output signal indicating the cpu is being reset . it can be used as a system reset. rfsh_n rf sh_n 64 7 26 r e f re sh. output. rfsh_n is asserted low to indicate a refresh bus cycle . s0_n s0_n 52 23 40 s tatus [ 2 : 0 ] _n are outputs . during a bus cycle the status (i.e., type) of cycle is encoded on these lines as follows: s2_n s1_n s0_n bus cycle status 0 0 0 interrupt acknowledge 0 0 1 read i/o 0 1 0 write i/o 0 1 1 processor halt 1 0 0 queue instruction fetch 1 0 1 read memory 1 1 0 write memory 1 1 1 no bus activity s1_n s1_n 53 22 39 s2_n s2_n 54 21 38 s3 a16 / s3 68 3 21 s tatu s [ 6 : 3 ] are o utput s . bus cycle a19/s 6 a18/s 5 a17/s 4 a16/s 3 t 1 a19 a18 a17 a16 t 2 n 0 0 0 t 3 n 0 0 0 t w n 0 0 0 t 4 n 0 0 0 ____________ n = 0 for cpu bus cycle. n = 1 for dma or refresh cycle. s4 a17 / s4 67 4 22 s5 a18 / s5 66 5 23 s6 a19 / s6 65 6 24 srdy srdy 49 27 44 s ynchronous r ea dy . input. test_n test_n /busy 47 29 46 test . input. active low. when the test_n input is high (i.e., not asserted), it causes the ia18 8 xl to suspend operation during the execution of the wait instruction. opera tion resumes when the pin is sampled low (asserted). tmr in 0 tmr in 0 20 59 77 t i m e r 0 in put. input. depending on the timer mode programmed for timer 0, this input is used either as clock input or a control signal. tmr in 1 tmr in 1 21 58 76 t i m e r 1 i n put. input. depending on the timer mode programmed for timer 1, this input is used either as clock input or a control signal. ?
ia186xl/ia188xl data sheet 16 - bit microcontrollers july 6, 2011 ia211080711 - 09 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 36 of 75 1 - 88 8 - 824 - 4184 table 8. ia188xl pin/signal descriptions (continued) signal pin description name plcc p qfp lqfp tmr out 0 tmr out 0 22 5 7 75 t i m e r 0 out put. output. depending on the timer mode programmed for timer 0, this output can provide a single pulse or a repetitive waveform. tmr out 1 tmr out 1 23 56 74 t i m e r 1 out put. output. depending on the timer mode programmed for timer 1, this output can provide a single pulse or a repetitive waveform. ucs_n ucs_n 34 45 62 u pper c hip s elect. output. active low. this pin provides a chip select signal that will be asserted (low) whenever the address of a memory bus cycle is within the add ress space programmed for that output. v cc v cc 9, 43 33, 34, 72, 73 10, 11, 20, 50, 51, 61 power ( v cc ). this pin provides power for the ia18 8 xl device. it must be connected to a +5v dc power source. v ss v ss 26, 60 12, 13, 53 30, 31, 41, 70, 80 ground ( v ss ). this pin provides the digital ground (0v) for the ia186xl. it must be connected to a v ss board plane. wr_n wr_n / qs1 63 8 27 wr ite. output. active low. when asserted (low), wr_n indicates that data available on the data bus are to be latched int o the accessed memory or i/o device. x1 x1 59 16 32 x1 and x2 are inputs for the crystal x2 x2 58 17 33 ?
ia186xl/ia188xl data sheet 16 - bit microcontrollers july 6, 2011 ia211080711 - 09 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 37 of 75 1 - 88 8 - 824 - 4184 3. maximum ratings, thermal characteristics, and dc parameters for the innovasic semiconductor ia186xl and ia188xl microcontrollers, the absolute max imum ratings, thermal characteristics, and dc parameters are provided in tables 9 through 11, respectively. table 9 . ia186xl and ia188xl absolute maximum ratings parameter rating storage temperature ? 40 c to +1 25 c supply voltage with respect to v ss ?0. 3 v to +6. 0 v voltage on pins other than supply with respect to v ss ?0. 3 v to +(vcc + 0. 3 )v table 10 . ia186xl and ia188xl thermal characteristics symbol characteristic value units t a ambient temperature - 40 c to 85 c c p d power dissipation mhz icc v/1000 w ja 68 - lead plcc package 32 c/w 80 - lead pqfp package 46 80 - lead lqfp package 52 t j average junction temperature t a + (p d ja ) c ?
ia186xl/ia188xl data sheet 16 - bit microcontrollers july 6, 2011 ia211080711 - 09 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 38 of 75 1 - 88 8 - 824 - 4184 table 11 . ia186xl and ia188xl d c parameters symbol parameter min max units notes 5.0 volt operation v cc supply voltage 4.5 5.5 v C v il input low voltage ?0. 3 0. 3 v cc v input hysteresis on resin_n = 0.50v v ih input high voltage 0.7 v cc v cc + 0. 3 v _ v ol output low voltage v cc = 5.0v C 0 . 4 v i ol = 12 ma v oh output high voltage v cc = 4.5v 3.5 - v i oh = ? 12 ma i l eak input leakage current for pins: ad 0 - ad 15 , ad 0 - ad 7 (ia188xl), resin_n, clkin, t0in_in, t1in_in, drq0, drq1, int0, int1, rmi, hold, srdy, ardy, int2_inta0_n, int3_inta1_n C 1 a 0v v in v cc input leakage current for pin (@5v): ucs_n, lcs_n, mcs0_n_pereq, mcs1_n_error_n, rd_n, test_n_busy - .227 - .833 ma v in = 0v i lo output leakage current C 10 a 0.45v v out v cc i id supply current (idle) - @ 50 mhz - 90 ma - c in input pin capacitance 0 5 pf t f = 1 mhz c out output pin capacitance 0 5 pf t f = 1 mhz operating temperature is ? 40 c to 85 c . ?
ia186xl/ia188xl data sheet 16 - bit microcontrollers july 6, 2011 ia211080711 - 09 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 39 of 75 1 - 88 8 - 824 - 4184 4. functional description the follow descriptions apply to both the ia186xl and ia188xl unless otherwise noted. m odule de scriptions are followed by descriptions of special operating modes. additional information on the operation and programming of the 80c186xl/80c188xl can be found in the following intel ? publications: 80c186xl/80c188xl and 80l186xl/80l188xl 16 - bit high - int egration embedded processors (272433 - 006) 80c186xl/80c188xl microprocessor users manual (270830 - 00n) 4.1 device architecture architecturally, the ia186xl microcontrollers include the following functional modules: bus interface unit clock generator interrupt control unit timer/counter unit chip - select unit refresh control unit power - save control dma unit a functional block diagram of the ia186xl/ia188xl is shown in figure 10. descriptions of the functional modules are provided in the follow subsections. c ontrol registers for the peripheral modules are located in a 256 byte control block. this block can be mapped to either memory or i/o space. the offset map for addressing these registers is given in table 12. 4.1.1 bus interface unit a local bus controller ge nerates the local bus control signals. it also employs a hold/hlda protocol for relinquishing the local bus to other bus masters. its outputs can be used to enable external buffers and to direct the flow of data on and off the local bus. the bus control ler is responsible for generating 20 bits of addre ss, read and write strobes, bus - cycle status information and data. this controller is also responsible for reading data from the local bus during a read operation. synchronous and asynchronous ready input pins are provided to extend a bus cycle beyond the minimum four clocks. the bus controller also generates two control signals (den_n ?
ia186xl/ia188xl data sheet 16 - bit microcontrollers july 6, 2011 ia211080711 - 09 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 40 of 75 1 - 88 8 - 824 - 4184 and dt/r_n) when interfacing to external transceiver chips. this capability allows the addition of transceivers for simp le buffering of the multiplexed address/data bus. during reset , the local bus controller performs the following actions: 1. floats ad0 C 15 (ad0 C 8), a16 C 19 (a9 C a19), bhe_n (rfsh_n), dt/r_n 2. drives ale low 3. drives hlda low 4. drives lock_n high and then float s 5. drive s den_n, rd_n , and wr_n high for one clock cycle, then float s them 6. drives s0_n , s1_n and s2_n to the inactive state (all high) and then float s them ?
ia186xl/ia188xl data sheet 16 - bit microcontrollers july 6, 2011 ia211080711 - 09 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 41 of 75 1 - 88 8 - 824 - 4184 figure 10 . ia186xl/ia188xl functional block diagram ?
ia186xl/ia188xl data sheet 16 - bit microcontrollers july 6, 2011 ia211080711 - 09 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 42 of 75 1 - 88 8 - 824 - 4184 the rd_n/qsmd_n, ucs_n, lc s_n, mcs0_n/pereq, mcs1_n/error_n, and test_n/busy pins include internal pull - ups that are active while res_n is applied. the state of these pins during reset controls invoking various alternative operating modes as described below: 1 once mode C ucs_n and lcs_n driven low. 2 enhanced mode C test_n/busy driven low then high. 3 queue status mode C rd_n/qsmd_n driven low. 4.1.2 clock generator the ia186xl/ia188xl uses an on - chip clock generator to supply internal and external clocks. the clock generator makes use of a crystal oscillator and includes a divide - by - two counter. figure 11 shows the various operating modes of the clock circuit. the clock circuit can use either a parallel resonant fundamenta l mode crystal network ( a ) or a third - overton e mode crystal network ( b), or it can be driven by an external clock source ( c). the following parameters are recommended when choosing a crystal: temperature range: application specific esr (equivalent series resistance): 60 max c0 (shunt capacitance of crystal): 7.0 pf max cl (load capacitance): 20 pf 2 pf drive level: 2 mw max 4.1.3 interrupt control unit the ia186xl operates with several interrupt sources. a separate interrupt control unit manages all sources based on priority to be individually handled by the cpu. the dma and timers produce internally generated requests. there are five externally generated interrupts - a single nmi and 4 others. 4.1.4 timer/counter unit there are three programmable internal timers in the ia186xl. tw o are very flexible and can be configured for many tasks. each of these has a single input used for either control or clocking, and a single output to generate waveforms. the third timer is simpler and can only be clocked from an internal source. it can be used for simple timing applications. it can also be used as a prescaler to the other two timers or as a trigger for dma requests. ?
ia186xl/ia188xl data sheet 16 - bit microcontrollers july 6, 2011 ia211080711 - 09 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 43 of 75 1 - 88 8 - 824 - 4184 figure 11 . clock circuit connection options 4.1.5 chip - select/ready generation logic the ia186xl pr ovides programmable chip - select generation for memories and peripherals. the chip can be programmed to provide ready or wait state generation. it can also provide latched address bits a1 and a2. chip select behavior is the same whether the access is gen erated by the cpu or the dma. a total of 6 chip selects are dedicated for different memory ranges. a single select for upper memory (ucs_n) , with a fixed end address of 0ffffh, is good for use as system memory since the reset vector points to ffff0h. a single select for lower memory (lcs_n) , with a fixed start address of 0h, is good for interrupt vectors which reside beginning at address 00000h. there are also four selects for anywhere else (exclusive of ucs_n and lcs_n areas) in the 1 mbyte memory in the user - locatable memory block. for the middle chip selects , the base address and block size are programmable, while only the block size for the upper and lower chip selects are programmable. seven additional chip selects can be programmed to access eit her peripherals or memory in seven contiguous fixed blocks of 128 bytes each. a single base address is programmable for these chip selects. ?
ia186xl/ia188xl data sheet 16 - bit microcontrollers july 6, 2011 ia211080711 - 09 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 44 of 75 1 - 88 8 - 824 - 4184 a programmable number of wait states (0 - 3) can be used to generate an internal ready for each chip select range. the ia186xl can be programmed to use or not use the external ready signal with or without the internal wait states from the internal ready being factored in. at reset, the chip - select/ready logic will be configured as follows: 1. all chip - select outputs will be driven high 2. exiting reset, the ucs control register (umcs) is set to fffbh, providing chip select to a 1 - kbyte block of memory with 3 wait states in combined with external ready. 3. all other chip select control registers are undefined after reset. the c pu must configure these control registers before the corresponding chips selects will become active. 4.1.6 d ma the ia186xl includes a dma controller with two channels. transfers can occur between any combination of memory and i/o space, to either odd or even address. data size can be either 8 or 16 bits, except on the ia188xl it can only be 8 bits. there are separate 20 - bit source and destination pointers for each channel. these pointers can be configured to increment, decrement or stay static after each transfer. for word transfers, pointers are incremented or decrement by two and for byte transfers, by one. one bus cycle is required to fetch data and one cycle to deposit it. 4.1.7 dram refresh control unit when in enhanced mode, the ia186xl supports dram r efresh cycles. reads are automatically generated at a programmable time interval. if enabled, chip selects are active for these reads. 4.1.8 power - save control when in enhanced mode, the ia186xl supports a power save mode of operation. the internal clock fre quency is divided by a programmable amount. this affects all internal logic including, timers, the refresh control unit and clkout generation. timers and the refresh control unit need to be reprogrammed accordingly when going in and out of power save if you wish to maintain the same real time references. ?
ia186xl/ia188xl data sheet 16 - bit microcontrollers july 6, 2011 ia211080711 - 09 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 45 of 75 1 - 88 8 - 824 - 4184 4.2 operating modes during reset the ia186xl can be configured to enable special operating modes described as follows. 4.2.1 enhanced mode if enhanced mode is enabled, the ia186xl has dram refresh, power - save and coprocessor support available in addition to the normal features available in compatible mode. enhanced mode will be invoked automatically if a coprocessor is attached. it can also be entered by tying the reset output to the test_n/busy input. an inter nal pull - up keeps the part from entering enhanced mode during normal operation. when not in enhanced mode, none of the enhanced mode registers can be accessed. queue - status functions, except for the coprocessor support, will be available when not in enha nced mode. 4.2.2 queue status mode when queue status mode is enabled, information about the instruction queue is output on the ale/qs0 and wr_n/qs1 pins. to enter queue status mode, the rd_n input should be tied low. it is sampled at reset, and if low, queue status mode is entered. an internal pull - up keeps the part from entering queue status mode during normal operation. 4.2.3 once mode once mode is a special test mode where all pins are set to a high impedance state. once mode is entered by forcing lcs_n and ucs_n low during reset. these pins are sampled on the rising edge of res but should be held low for at least a full clock cycle after res goes high. once mode is exited by reseting the part with lcs_n and ucs_n high. internal pull - ups keep the part from entering once mode during normal operation. 4.2.4 math coprocessor (ia186xl only) when enhanced mode is enabled, the ia186xl is configured to interface with a math coprocessor via three of the middle chip select pins. pin mcs0/pereq is used for processor exte nsion request. pin mcs1/error is used for coprocessor error indication. pin mcs3/nps is used for numeric processor select. ?
ia186xl/ia188xl data sheet 16 - bit microcontrollers july 6, 2011 ia211080711 - 09 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 46 of 75 1 - 88 8 - 824 - 4184 table 12 . internal register map pcb offset function pcb offset function pcb offset function pcb offs et function 00h reserved 40h reserved 80h reserved c0h d0srcl 02h reserved 42h reserved 82h reserved c2h d0srch 04h reserved 44h reserved 84h reserved c4h d0dstl 06h reserved 46h reserved 86h reserved c6h d0dsth 08h reserved 48h reserved 88h reserved c8h d0tc 0ah reserved 4ah reserved 8ah reserved cah d0con 0ch reserved 4ch reserved 8ch reserved cch reserved 0eh reserved 4eh reserved 8eh reserved ceh reserved 10h reserv ed 50h t0cnt 90h reserved d0h d1srcl 12h reserved 52h t0cmpa 92h reserved d2h d1srch 14h reserved 54h t0cmpb 94h reserved d4h d1dstl 16h reserved 56h t0con 96h reserved d6h d1dsth 18h reserved 58h t1cnt 98h reserved d8h d1tc 1ah reserved 5ah t1cmpa 9ah reserved dah d1con 1ch reserved 5ch t1cmpb 9ch reserved dch reserved 1eh reserved 5eh t1con 9eh reserved deh reserved 20h reserved 60h t2cnt a0h umcs e0h rfbase 22h eoi 62h t2cmpa a2h lmcs e2h rftime 24h poll 64h reserved a4h pacs e4h rfcon 26h pollsts 66h t2con a6h mmcs e6h reserved 28h imask 68h reserved a8h mpcs e8h reserved 2ah primsk 6ah reserved aah reserved eah reserved 2ch inserv 6ch reserved ach reserved ech reserved 2eh reqst 6eh reserved aeh reserved eeh reserved 30h insts 70h reserved b0h reserved f0h pwrsav 32h tcucon 72h reserved b2h reserved f2h pwrcon 34h dma0con 74h reserved b4h reserved f4h reserved 36h dma1con 76h reserved b6h reserved f6h step id 1 38h i0con 78h reserved b8h reserved f8h reserved 3ah i1con 7ah reserved bah reserved fah reserved 3ch i2con 7ch reserved bch reserved fch reserved 3eh i3con 7eh reserved beh reserved feh relreg note: 1 the step id register (offset 0xf6) for revision 1 of the innovasic device is read - only, and is uniquely identified in software by having a va lue of 0x0081. the original intel device established a value between 0x0000 and 0x0003, depending on the revision of the part. ?
ia186xl/ia188xl data sheet 16 - bit microcontrollers july 6, 2011 ia211080711 - 09 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 47 of 75 1 - 88 8 - 824 - 4184 5. ac specifications 5.1 major cycle timings C read cycle t a = - 40 ? c to + 85 ? c, v cc = 5v + 10% all timings are measured at 1.5v and 50 pf loading on clkout unless otherwise noted. all output test conditions are with c l = 50 pf. for ac tests, input v il = 0.45v and v ih = 2.4v except at x1 where v ih = v cc C 0.5v. table 13 . major cycle timings C read cycle symbol parameter values unit test conditions min max t dvcl data in setup (a / d) 8 ns t cldx data in hold (a / d) 3 ns t chsv status active delay 3 20 ns t c h sh status inacti ve delay 3 20 ns t clav address valid delay 3 20 ns t clax address hold 0 ns t cldv data valid delay 3 20 ns t chdx status hold time 10 ns t chlh ale active delay 20 ns t lhll ale width t clcl - 15 ns t chll ale inactive delay 20 ns t avll address valid to ale low t clch - 10 ns equal loading t llax address hold from ale inactive t chcl - 8 ns equal loading t avch address valid to clock high 0 ns t claz address float delay t clax 20 ns t clcsv chip - select active delay 3 20 ns t cxcsx chip - select hold from command inactive t clch - 10 ns equal loading t chcsx chip - select inactive delay 3 17 ns t dxdl den inactive to dt / r low 0 ns equal loading t cvctv control active delay 1 3 17 ns t cvdex den inactive d elay 3 17 ns t chctv control active delay 2 3 20 ns t cllv lock valid / invalid delay 3 17 ns t azrl address float to rd active 0 ns t clrl rd active delay 3 20 ns t rlrh rd pulse width 2 tclcl - 15 ns t clrh rd inactive delay 3 20 ns t rhlh rd inactive to ale high t clch - 14 ns equal loading ?
ia186xl/ia188xl data sheet 16 - bit microcontrollers july 6, 2011 ia211080711 - 09 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 48 of 75 1 - 88 8 - 824 - 4184 t rhav rd inactive to address active t clcl - 15 ns equal loading figure 12 . read cycle waveforms t chsh (1) (2) please note that pins indicated in the parentheses are for the ia188xl version. notes: (1) the oem part (80c186xl) operates differently in that it deasserts on the falling edge of clkout. (2) status is inactive in the state preceding t4. (3) only tclcsv is applicable if latched a1 and a2 are selected instead of pcs5 and pcs6. (4) this applies when a write cycle is followed by read cycle. (5) this is t1 of next bus cycle. (6) this changes in the t - st ate preceding the next bus cycle if followed by a write. ( 3 ) ( 4 ) ( 5 ) ( 6 ) ?
ia186xl/ia188xl data sheet 16 - bit microcontrollers july 6, 2011 ia211080711 - 09 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 49 of 75 1 - 88 8 - 824 - 4184 5.2 major cycle timings C write cycle t a = - 4 0 ? c to + 85 ? c, v cc = 5v + 10% all timings are measured at 1.5v and 50 pf loading on clkout unless otherwise noted. all output test conditions are with c l = 50 pf. for ac tests, input v il = 0.45v and v ih = 2.4v except at x1 where v ih = v cc C 0.5v. table 14 . major cycle timings C write cycle symbol parameter values unit test conditions min max t chsv status active delay 3 20 ns t c h sh status inactive delay 3 20 ns t clav address valid delay 3 20 ns t clax addr ess hold 0 ns t cldv data valid delay 3 20 ns t chdx status hold time 10 ns t chlh ale active delay 20 ns t lhll ale width t clcl - 15 ns t chll ale inactive delay 20 ns t avll address valid to ale low t clch - 10 ns equal loading t llax address hold from ale inactive t chcl - 10 ns equal loading t avch address valid to clock high 0 ns t cldox data hold time 3 ns t cvctv control active delay 1 3 20 ns t cvctx control inactive delay 3 17 ns t clcsv chip - select active d elay 3 20 ns t cxcsx chip - select hold from command inactive t clch - 10 ns equal loading t chcsx chip - select inactive delay 3 17 ns t dxdl den inactive to dt / r low 0 ns equal loading t cllv lock valid / invalid delay 3 17 ns t wlwh wr pulse wid th 2 tclcl - 15 ns t whlh wr inactive to ale high t clch - 14 ns equal loading t whdx data hold after wr t clcl - 10 ns equal loading t whdex wr inactive to den inactive t clch - 10 ns equal loading ?
ia186xl/ia188xl data sheet 16 - bit microcontrollers july 6, 2011 ia211080711 - 09 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 50 of 75 1 - 88 8 - 824 - 4184 figure 13 . write cycle waveforms please note that pins indicated in the parentheses are fo r the ia188xl version. notes: (1) the oem part (80c186xl) operates differently in that it deasserts on the falling edge of clkout. (2) status is inactive in the state preceding t4. (3) only tclcsv is applicable if latched a1 and a2 are selected instead of pcs5 and pc s6. (4) this applies when a write cycle is followed by a read cycle. (5) this is t1 of next bus cycle. (6) this changes in the t - state preceding the next bus cycle if followed by a read, inta or halt. t chsh (1) (2) ( 6 ) ( 5 ) ( 3 ) ( 4 ) ?
ia186xl/ia188xl data sheet 16 - bit microcontrollers july 6, 2011 ia211080711 - 09 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 51 of 75 1 - 88 8 - 824 - 4184 5.3 major cycle timings C interrupt acknowledge cycle t a = - 4 0 ? c to + 85 ? c, v cc = 5v + 10% all timings are measured at 1.5v and 50 pf loading on clkout unless otherwise noted. all output test conditions are with c l = 50 pf. for ac tests, input v il = 0.45v and v ih = 2.4v except at x1 where v ih = v cc C 0.5v. table 15 . major cycle timings C interrupt acknowledge cycle symbol parameter values unit test conditions min max t dvcl data in setup (a / d) 8 ns t cldx data in hold (a / d) 3 ns t chsv status active delay 3 20 ns t c h sh status inactive delay 3 20 ns t clav address valid delay 3 20 ns t avch address valid to clock high 0 ns t clax address hold 0 ns t cldv data valid delay 3 20 ns t chdx status hold time 10 ns t chlh ale active delay 20 ns t lhl l ale width t clcl - 15 ns t chll ale inactive delay 20 ns t avll address valid to ale low t clch - 10 ns equal loading t llax address hold to ale inactive t chcl - 10 ns equal loading t claz address float delay t clax 20 ns t cvctv control a ctive delay 1 3 17 ns t cvctx control inactive delay 3 17 ns t dxdl den inactive to dt / r low 0 ns equal loading t chctv control active delay 2 3 20 ns t cvdex den inactive delay (non - write cycles) 3 17 ns t cllv lock valid / invalid delay 3 1 7 ns ?
ia186xl/ia188xl data sheet 16 - bit microcontrollers july 6, 2011 ia211080711 - 09 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 52 of 75 1 - 88 8 - 824 - 4184 figure 14 . interrupt acknowledge cycle waveforms t chsh (1) (2) ( 3 ) ( 4 ) ( 5 ) ( 6 ) ( 7 ) please note that pins indicated in the parentheses are for the ia188xl version. notes: (1) the oem part (80c186xl) operates differently in that it deasserts on the falling edge of clkout. (2) status is inactive in the state preceding t4. (3) the data hold time lasts only until inta goes inactive, even if the inta transition occurs prior to tcldx (min). (4) inta occurs one clock later in slave mode. (5) this applies when a write cycle is followed by an interrupt acknowledge cycle. (6) lock is active upon t1 of the first interrupt acknowledge cycle, and inactive upon t2 of the second interrupt acknowledge cycle. (7) changes in t - state preceding next bus cycle if followed by write. ?
ia186xl/ia188xl data sheet 16 - bit microcontrollers july 6, 2011 ia211080711 - 09 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 53 of 75 1 - 88 8 - 824 - 4184 5.4 software halt cycle timings t a = - 4 0 ? c to + 85 ? c, v cc = 5v + 10% all timings are measured at 1.5v and 50 pf loading on clkout unless otherw ise noted. all output test conditions are with c l = 50 pf. for ac tests, input v il = 0.45v and v ih = 2.4v except at x1 where v ih = v cc C 0.5v. table 16 . software halt cycle timings symbol parameter values unit test condi tions min max t chsv status active delay 3 20 ns t c h sh status inactive delay 3 20 ns t clav address valid delay 3 20 ns t chlh ale active delay 20 ns t lhll ale width t clcl - 15 ns t chll ale inactive delay 20 ns t dxdl den ina ctive to dt / r low 0 ns equal loading t chctv control active delay 2 3 20 ns ?
ia186xl/ia188xl data sheet 16 - bit microcontrollers july 6, 2011 ia211080711 - 09 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 54 of 75 1 - 88 8 - 824 - 4184 figure 15 . software halt cycle waveforms please note that pins indicated in the parentheses are for the ia188xl version. notes: (1) the oem part (80c186xl) operates differently in that it deasserts on the falling edge of clkout. ( 2 ) this applies when a write cycle is followed b y a halt cycle . ( 2 ) t chsh (1) ?
ia186xl/ia188xl data sheet 16 - bit microcontrollers july 6, 2011 ia211080711 - 09 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 55 of 75 1 - 88 8 - 824 - 4184 5.5 clock timings t a = - 4 0 ? c to + 85 ? c, v cc = 5v + 10% all timings are measured at 1.5v a nd 50 pf loading on clkout unless otherwise noted. all output test conditions are with c l = 50 pf. for ac tests, input v il = 0.45v and v ih = 2.4v except at x1 where v ih = v cc C 0.5v. table 17 . clock timings symbol parameter v alues unit test conditions min max t ckin clkin period 20 ns t clck clkin low time 8 ns 1 . 5v(2) t chck clkin high time 8 ns 1 . 5v(2) t ckhl clkin fall time 5 ns 3 . 5 to 1 . 0v t cklh clkin rise time 5 ns 1 . 0 to 3 . 5v t cico clkin to clkout skew 17 ns t clcl clkout period 40 ns t clch clk out low time 0 . 5 t clcl - 5 ns c l = 100 pf(3) t chcl clkout high time 0 . 5 t clcl - 5 ns c l = 100 pf(4) t ch1ch2 clkout rise time 6 ns 1 . 0 to 3 . 5v t cl2cl1 clkout fall time 6 ns 3 . 5 to 1 . 0v notes : 1. external clock applied to x1 and x2 not conn ected . 2. t clck and t chck (clkin low and high times) should not have a duration less than 40% of t ckin . 3. tested under worst case conditions : v cc = 5 . 5v . t a = 70 ? c . 4. tested under worst case conditions : v cc = 4 . 5v . t a = 0 ? c . ?
ia186xl/ia188xl data sheet 16 - bit microcontrollers july 6, 2011 ia211080711 - 09 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 56 of 75 1 - 88 8 - 824 - 4184 5.6 ready, peripheral and queue status timings t a = - 4 0 ? c to + 85 ? c, v cc = 5v + 10% all timings are measured at 1.5v and 50 pf loading on clkout unless otherwise noted. all output test conditio ns are with c l = 50 pf. for ac tests, input v il = 0.45v and v ih = 2.4v except at x1 where v ih = v cc C 0.5v. table 18 . ready, peripheral and queue status timings symbol parameter values unit test conditions min max t sr ycl synchronous ready (srdy) transition setup time(1) 8 ns t clsry srdy transition hold time(1) 8 ns t arych ardy resolution transition setup time(2) 8 ns t clarx ardy active hold time(1) 8 ns t arychl ardy inactive holding time 8 ns t arylcl asynchronous ready (ardy) setup time(1) 10 ns t invch intx , nmi , test , busy , tmr in setup time(2) 8 ns t invcl drq0 , drq1 setup time(2) 8 ns t cltmv timer output delay 17 ns t chqsv queue status delay 22 ns notes : 1. to guarantee proper operation . 2. to guarantee recognition at clock edge . ?
ia186xl/ia188xl data sheet 16 - bit microcontrollers july 6, 2011 ia211080711 - 09 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 57 of 75 1 - 88 8 - 824 - 4184 5.7 reset and hold/hlda timings t a = - 4 0 ? c to + 85 ? c, v cc = 5v + 10% all timings are measured at 1.5v and 50 pf loading on clkout unless otherwise noted. all output test conditions are with c l = 50 pf. for ac tests, input v il = 0.45v and v ih = 2.4v except at x1 where v ih = v cc C 0.5v. table 19 . reset and hold/hlda timings symbol parameter values unit test conditions min max t resin res setup 15 ns t hvcl hold setup(1) 8 ns t claz address float delay t clax 20 ns t clav address valid delay 3 20 ns t clro reset delay 17 ns t clhav hlda valid delay 3 17 ns t chcz command lines float delay 22 ns t chcv command lines valid delay (after float) 20 ns note : 1. to guarantee recognition at next clock . ?
ia186xl/ia188xl data sheet 16 - bit microcontrollers july 6, 2011 ia211080711 - 09 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 58 of 75 1 - 88 8 - 824 - 4184 figure 16 . clock waveforms figure 17 . reset waveforms figure 18 . synchronous ready (srdy) waveforms ?
ia186xl/ia188xl data sheet 16 - bit microcontrollers july 6, 2011 ia211080711 - 09 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 59 of 75 1 - 88 8 - 824 - 4184 figure 19 . asynchronous ready (ardy) waveforms figure 20 . peripheral and queue status waveforms ?
ia186xl/ia188xl data sheet 16 - bit microcontrollers july 6, 2011 ia211080711 - 09 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 60 of 75 1 - 88 8 - 824 - 4184 figure 21 . holda/hlda waveforms (entering hold) figure 22 . hold/hlda waveforms (leaving hold) ?
ia186xl/ia188xl data sheet 16 - bit microcontrollers july 6, 2011 ia211080711 - 09 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 61 of 75 1 - 88 8 - 824 - 4184 6. instruc tion execution times table 20 provides ia186xl and ia188xl execution times, mnemonic instruction, and additional information on execution, if required. table 20 . instruction set timing instruction clock cycles comments ia186xl i a188xl aaa 3 3 C aad 6 6 C aam 40 40 C aas 3 3 C adc immediate to accumulator 1 1 C adc immediate to register/memory 3 13 C register/memory adc register/memory with register to either 1/16 1/24 add immediate to accumulator 1 1 C add immediate t o register/memory 1/19 1/32 register/memory add register/memory with register either 1/20 1/28 and immediate to accumulator 1 1 C and immediate to register/memory 1/24 1/33 register/memory and register/memory and register to either 1/12 1/15 bound 2 0/40 24/64 interrupt not taken/interrupt taken cbw 1 4 C clc 1 1 C cld 1 1 C cli 1 1 C cmc 2 2 C cmps 9 20 C cs 1 1 C cwd 1 1 C daa 4 4 C das 2 2 C dec register 1 1 C dec register/memory 1/24 1/32 register/memory ?
ia186xl/ia188xl data sheet 16 - bit microcontrollers july 6, 2011 ia211080711 - 09 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 62 of 75 1 - 88 8 - 824 - 4184 table 20 . instruction set t iming (continued) instruction clock cycles comments ia186xl ia188xl div memory - byte 46 46 C div memory - word 49 51 C div register - byte 39 39 C div register - word 39 39 C idiv memory - byte 46 46 C idiv memory - word 49 51 C idiv register - byte 39 39 C idiv register - word 39 39 C imul immediate (signed) 5/24 5/33 register/memory imul memory - byte 4 20 C imul memory - word 13 28 C imul register - byte 5 5 C imul register - word 5 5 C inc register 1 1 C ins 8 16 C ins (repeated n times) 8+8 n 16+16 n C int type specified 33 41 C int type 3 33 41 C into 33 48 C iret 30 30 C ja 3/5 3/5 jump not taken/jump taken jae 3/5 3/5 jb 3/5 3/5 jbe 3/5 3/5 jcxz 3/4 3/4 jump not taken/jump taken je 3/5 3/5 jump not taken/jump taken jg 3/5 3/5 jge 3/5 3/5 jl 3/5 3/5 jle 3/5 3/5 jmp direct intersegment 3 3 C jmp direct within segment 3 3 C jmp short/long 4 4 C jna 3/5 3/5 jump not taken/jump taken jnae 3/5 3/5 jnb 3/5 3/5 jnbe 3/5 3/5 jne 3/5 3/5 jng 3/5 3/5 jnge 3/5 3/5 jnl 3/5 3/5 jnl e 3/5 3/5 jno 3/5 3/5 jnp 3/5 3/5 ?
ia186xl/ia188xl data sheet 16 - bit microcontrollers july 6, 2011 ia211080711 - 09 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 6 3 of 75 1 - 88 8 - 824 - 4184 table 20 . instruction set timing (continued) instruction clock cycles comments ia186xl ia188xl jns 3/5 3/5 jump not taken/jump taken jnz 3/5 3/5 jo 3/5 3/5 jp 3/5 3/5 jpe 3/5 3/5 jpo 3/5 3/5 js 3/5 3 /5 jz 3/5 3/5 lahf 2 2 C lds 1/24 1/33 register/memory lea 3 3 C leave 12 12 C les 12 32 C lock 1 1 C lods 8 12 C lods (repeated n times) 8+8 n 12+12 n C loop 3/4 3/4 loop not taken/loop taken loope 3/4 3/4 loop not taken/loop taken loopne 3/4 3/4 loopnz 3/4 3/4 loopz 3/4 3/4 mov accumulator to memory 5 8/12 8 - bit/16 - bit mov immediate to register 1 1 - mov immediate to register/memory 1/5 1/12 register/memory mov memory to accumulator 5 8/12 8 - bit/16 - bit mov register to register/memory 2/5 2/20 register/memory mov register/memory to register 2/5 2/20 mov register/memory to segment register 2/5 2/20 mov segment register to register/memory 2/5 2/20 movs 24 32 C movs (repeated n times) 24+24 n 32+32 n C mul memory - byte 16 20 C mul memory - word 15 25 C mul register - byte 5 5 C mul register - word 5 5 C neg 1/32 1/15 register/memory nop 1 1 C not 1/24 1/24 register/memory or immediate to accumulator 1 1 C ?
ia186xl/ia188xl data sheet 16 - bit microcontrollers july 6, 2011 ia211080711 - 09 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 64 of 75 1 - 88 8 - 824 - 4184 table 20 . instruction set timing (continued) instruction clock cycles comme nts ia186xl ia188xl or immediate to register/memory 1/32 1/32 register/memory or register/memory and register to either 1/32 1/24 out fixed port 5 8/12 8 - bit/16 - bit out variable port 5 12 C outs 8 12/20 8 - bit/16 - bit outs (repeated n times) 8+8 n 1 2/20+12/20 n 8 - bit/16 - bit pop memory 10 20 C pop register 10 12 C pop segment register 16 12 C popa 80 93 C popf 13 13 C push immediate 8 12 C push memory 15 28 C push register 4 12 C push segment register 4 12 C pusha 64 72 C pushf 4 16 C ret i nter - segment 14 21 C ret inter - segment adding immediate to sp 25 21 C ret within segment 14 13 C ret within segment adding immediate to sp 16 13 C rol register/memory by 1 1/8 1/16 register/memory rol register/memory by cl 1/8 1/16 rol register/memo ry by count 1/8 1/24 ror register/memory by 1 1/8 1/16 ror register/memory by cl 1/8 1/16 ror register/memory by count 1/8 1/24 sahf 2 2 C sbb immediate from accumulator 1 1 C sbb immediate from register/memory 1/15 1/28 register/memory sbb regi ster/memory and register to either 1/11 1/40 register/memory scas 11 8/12 8 - bit/16 - bit scas (repeated n times) 11+8 n 8/12+8/12 n 8 - bit/16 - bit shl register/memory by 1 5 1/32 register/memory ?
ia186xl/ia188xl data sheet 16 - bit microcontrollers july 6, 2011 ia211080711 - 09 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 65 of 75 1 - 88 8 - 824 - 4184 table 20 . instruction set timing (continued) instruction cl ock cycles comments ia186xl ia188xl shl register/memory by cl 1/20 1/24 register/memory shl register/memory by count 1/11 1/24 shr register/memory by 1 1/5 1/24 shr register/memory by cl 1/20 1/28 shr register/memory by count 1/11 1/24 ss 1 1 C stc 1 1 C sub immediate from accumulator 1 1 - sub immediate from register/memory 1/11 1/28 register/memory sub register/memory and register to either 1/15 1/40 std 1 1 C sti 1 1 C stos 6 8 C stos (repeated n times) 6+4n 8+8n C test immediate d ata and accumulator 1 1 C test immediate data and register/memory 1/16 1/16 register/memory test register/memory and register 1/12 1/20 register/memory wait 1 1 test_n = 0 xchg register with accumulator 2 2 C xchg register/memory with register 3/16 3/ 20 register/memory xlat 16 8 C xor immediate to accumulator 1 1 C xor immediate to register/memory 1/11 1/32 register/memory xor register/memory and register to either 1/16 1/32 register/memory ?
ia186xl/ia188xl data sheet 16 - bit microcontrollers july 6, 2011 ia211080711 - 09 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 66 of 75 1 - 88 8 - 824 - 4184 7. innovasic part number cross - reference tables 21 through 23 cross - reference the innovasic part number with the corresponding intel part number . table 21 . innovasic part number cross - reference for the plcc innovasic part number intel part number package type temperature range ia186xlp lc 68 ir 1 (lead free C rohs) n80c186xl25 n80c186xl20 n80c186xl12 tn80c186xl25 tn80c186xl20 tn80c186xl12 ee80c186xl25 ee80c186xl20 ee80c186xl12 EN80C186XL20 en80c186xl12 68 - lead plcc industrial ia188xlplc 68 ir 1 (lead free C rohs) n80c188xl25 n80c188xl20 n80c188xl 12 tn80c188xl25 tn80c188xl20 tn80c188xl12 ee80c188xl25 ee80c188xl20 ee80c188xl12 en80c188xl20 en80c188xl12 68 - lead plcc industrial ?
ia186xl/ia188xl data sheet 16 - bit microcontrollers july 6, 2011 ia211080711 - 09 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 67 of 75 1 - 88 8 - 824 - 4184 table 22 . innovasic part number cross - reference for the pqfp (special order only) innovasic part number intel part number package type temperature range ia186xlpqf80ir 1 ( lead free C rohs) s80c186xl25 s80c186xl20 s80c186xl12 ts80c186xl25 ts80c186xl20 ts80c186xl12 eg80c186xl25 eg80c186xl20 es80c186xl20 80 - lead pqfp industrial ia188xlpqf80ir 1 ( lead free C rohs) s80c188xl25 s80c188xl20 s80c188xl12 ts80c188xl25 ts80c188xl20 ts80c188xl12 eg80c188xl25 eg80c188xl20 es80c188xl20 80 - lead pqf p industrial ?
ia186xl/ia188xl data sheet 16 - bit microcontrollers july 6, 2011 ia211080711 - 09 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 68 of 75 1 - 88 8 - 824 - 4184 table 23 . innovasic part number cross - reference for the lqfp (special order only) in novasic part number intel part number package type temperature range ia186xlplq80i r 1 (lead free C rohs) sb80c186xl25 sb80c186xl20 sb80c186xl12 yw80c186xl25 yw80c186xl20 80 - lead lqfp industrial ia188xlplq80ir 1 (lead free C rohs) sb80c188xl25 sb80c188xl20 sb80 c188xl12 yw80c188xl25 yw80c188xl20 80 - lead lqfp industrial ?
ia186xl/ia188xl data sheet 16 - bit microcontrollers july 6, 2011 ia211080711 - 09 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 69 of 75 1 - 88 8 - 824 - 4184 8. errata the following errata are associated with the ia186 xl /ia188 xl . a workaround to the identified problem has been provided where possible. 8.1 summary table 24 presents a summary of errata. table 24 . summary of errata errata no. problem ver. 0 ver. 1 ver. 2 1 pin lock_n does not have an internal pullup and will float during reset and bus hold . exists exists exists 2 when the timer compare register for any of the t imers is set to x0000, the max count is xffff instead of x10000 as in the oem part. exists fixed fixed 3 when using external interrupts irq0 or irq1 in cascade mode, the acknowledge signal on inta0 or inta1 may be lost or truncated. exists fixed fixed 4 memory - >memory moves interrupted by two dma cycles can corrupt data. exists fixed fixed 5 bit 15 of relreg (offset 0xfe) behaves differently than intel device. exists fixed fixed 6 enhanced mode makes bit 15 of relreg (offset 0xfe) read - only. exists fixe d fixed 7 sbus deasserts on the wrong edge of clkout. exists fixed fixed 8 timer2 count register must be written to enable counting . exists exists fixed 9 non - maskable interrupt (nmi) can be pre - empted by maskable interrupt . exists exists fixed 10 dma can hang . exists exists fixed ?
ia186xl/ia188xl data sheet 16 - bit microcontrollers july 6, 2011 ia211080711 - 09 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 70 of 75 1 - 88 8 - 824 - 4184 errata no. problem ver. 0 ver. 1 ver. 2 11 movs/pop/push instructions interrupted by dma can corrupt data . exists exists fixed 12 movs/pop/push instructions interrupted by dma can corrupt data . exists exists fixed 8.2 detail errata no. 1 pr oblem: pin lock_n does not have an internal pullup . description: because pin lock_n does not have an internal pullup , it will float during reset and bus hold . workaround: an external pullup may be necessary if there is high external load on the signal . errata no. 2 problem: when the timer compare register for any of the timers is set to x0000, the max count is xffff instead of x10000 as in the oem part. description: the timer output will change one count earlier than it should when the max count i s set to x0000. workaround: the workaround is application dependent. please contact innovasic technical support if this erratum is an issue . errata no. 3 problem: when using external interrupts irq0 or irq1 in cascade mode, the acknowledge signal on i nta0 or inta1 may be lost or truncated. description: the acknowledge for irq0 or irq1 will be lost or truncated in cascade mode if another interrupt, with a higher priority setting (as configured in the interrupt control registers), occurs just before o r during the acknowledge. this does not apply to interrupts generated by the dma. this also does not apply when using the inherent priority settings (all interrupts configured with the same priority). ?
ia186xl/ia188xl data sheet 16 - bit microcontrollers july 6, 2011 ia211080711 - 09 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 71 of 75 1 - 88 8 - 824 - 4184 workaround: when using external interrupts in casca de mode, do not program other interrupts to have a high priority (except dmas). when using both irq0 and irq1 in cascade mode they must be programmed to have the same priority level. errata no. 4 problem: memory - >memory moves interrupted by two dma cycl es can corrupt data . description: this problem occurs if memory - >memory operation is interrupted by 2 dma cycles with the following sequence: 1. the instruction reads data from memory. 2. the first dma cycle occurs. 3. the second dma request occurs between 1 a nd 4 clocks after the falling edge of ale for the deposit phase of the first dma. 4. an instruction fetch occurs (this will be the data that shows up later). 5. the second dma cycle occurs. 6. the write phase of the instruction happens with bad data (from step 4). if the second dma request occurs earlier than 1 clock after ale for the first dma's deposit phase, step 4 will be preempted by the second dma, and operation is correct. if the second dma request occurs later than 4 clocks after ale for the first dma's de posit phase, the write phase will follow step 4 immediately, and operation is correct. of the total 163 instructions, the following 8 are impacted by this issue, with both the 8 & 16 bit versions of the first 7 on the list being affected. 1. movs 2. push mem 3. p op mem 4. ins 5. in 6. outs 7. out 8. enter workaround: if the conditions described above occur, there is no workaround . however, this dma issue will be corrected in revision 1 of the device. ?
ia186xl/ia188xl data sheet 16 - bit microcontrollers july 6, 2011 ia211080711 - 09 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 72 of 75 1 - 88 8 - 824 - 4184 errata no. 5 problem: bit 15 of relreg (offset 0xfe) behaves differently than intel device. description: for both 188 and 186 devices , an esc opcode will generate a type 7 interrupt only when relreg[15] is a 0. workaround: initialize relreg[15] to 0 if a type 7 interrupt is desired. errata no. 6 problem: enhanced mode ma kes bit 15 of relreg (offset 0xfe) read - only. description: if the device comes out of reset in enhanced mode, relreg[15] will be set to a 1. workaround: avoid enhanced mode if a type 7 interrupt is desired. errata no. 7 problem: sbus deasserts on th e wrong edge of clkout. description: the sbus goes inactive (high) at the end of a bus cycle on the falling edge of clkout. it should be on the rising edge of clkout. workaround: none. errata no. 8 problem: timer2 count register must be written to e nable counting. description: if timer 2 count register is not explicitly written timer 2 will not count; this can also prevent timers 0 & 1 from counting if timer 2 is used as a prescaler. workaround: write timer 2 count register before enabling timer 2. ?
ia186xl/ia188xl data sheet 16 - bit microcontrollers july 6, 2011 ia211080711 - 09 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 73 of 75 1 - 88 8 - 824 - 4184 errata no. 9 problem: non - maskable interrupt (nmi) can be pre - empted by maskable interrupt . description: when instruction execution unit is in decode state for 2 or more consecutive cycles and an nmi is recognized, it could be pre - empted by a maska ble interrupt . workaround: none. errata no. 10 problem: dma can hang . description: dma to a region of memory using destination synchronization and a chip select with extra wait states can hang . workaround: do not use wait states and destination sy nchronization together . errata no. 11 problem: movs/pop/push instructions interrupted by dma can corrupt data . description: movs/pop/push instructions interrupted by both a dma transaction and an instruction fetch bus cycle can corrupt data . this affe cts the ia186xl only. workaround: none. errata no. 12 problem: movs/pop/push instructions interrupted by dma can corrupt data . description: movs/push/pop instructions with 16 - bit, non - aligned destination address interrupted by dma can corrupt data . this affects the ia186xl only. workaround: none. ?
ia186xl/ia188xl data sheet 16 - bit microcontrollers july 6, 2011 ia211080711 - 09 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 74 of 75 1 - 88 8 - 824 - 4184 9. data sheet revision history table 25 presents the sequence of revisions to document ia 21108 0711. table 25 . data sheet revision history date revision description page(s) septemb er 30, 2008 00 initial release na august 5 , 2009 01 updated dc parameters; updated ac specifications and timing diagrams; updated instruction set timing; added errata. multiple pages throughout the document august 19, 2009 02 final version of the data sh eet released to support production of version 0 of the ia186/188 xl. release date changed, preliminary removed from heading and document number revised to reflect final release. no other changes. headers and footers on all pages september 4, 2009 03 updated the package dimensions table for the 68 plcc ; added a note to table 12 regarding the step id register ; updated errata 4 to include more recent information. 14, 46, 69, 71 january 15, 2010 04 updated ac and dc table notes to show t a at industrial t emperature instead of commercial; updated errata information for version 1 of the device ; updated note regarding stepid register. 46, 47, 49, 51, 53, 55, 56, 57, 69 january 12, 2011 05 updated to add errata 8. 69, 72 january 13, 2011 06 updated to add err ata 9 C 12 . 69 - 73 march 23, 2011 07 updated instruction set timing table to incorporate div and idiv values. 62 june 30, 2011 08 updated errata table to note fixes in ver. 2. 69, 70 july 6, 2011 09 updated pin descriptions for inputs/outputs. 25, 28, 31, 32, 34 ?
ia186xl/ia188xl data sheet 16 - bit microcontrollers july 6, 2011 ia211080711 - 09 http://www.innovasic.com uncontrolled when pr inted or copied customer support: page 75 of 75 1 - 88 8 - 824 - 4184 10. for additional information the innovasic semiconductor ia186xl and ia188xl microcontrollers are form, fit, and function replacements for the original intel 80c186xl and 80c188xl 16 - bit high - integration embedded processors. the innovasic supp ort team wants our information to be complete, accurate, useful, and easy to understand. please feel free to contact our experts at innovasic at any time with suggestions, comments, or questions. innovasic support team 3737 princeton ne suite 130 albuquer que, nm 87107 (505) 883 - 5263 fax: (505) 883 - 5477 toll free: (888) 824 - 4184 e - mail: support@innovasic.com website : http://www.innovasic.com ?

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